For communication between a host device and an external peripheral device, it is known to use a memory mapped interface between the host device and the peripheral device, e.g., a PCIe (Peripheral Components Interconnect Express) interface. Using the memory mapped interface, the peripheral device can directly write data into a memory of the host device or read data from the memory of the host device. In this way, the peripheral device may efficiently communicate with one or more processes executed by the host device.
For communication from the peripheral device to two processes executed by the host device, the memory of the processor device may be configured with a corresponding interface memory ring for each of the processes. The peripheral device may then transfer data to a given one of the processes by writing the data into the corresponding interface memory ring. However, configuring multiple interface memory rings may result in inefficient utilization of resources. Another possibility would be to utilize just one interface memory ring, from which one of the two processes, referred to as master process, copies the data intended for the other process into a further memory ring. However, the latter option may cause additional latency for the other process.
Accordingly, there is a need for techniques which allow for efficient communication of data between a processor device and an external peripheral device.